The present invention pertains to reliable computer memory arrangement and more particularly to an arrangement for column sparing of memory units.
Memory reliability is a critical issue in many computer systems and is of particular importance in computer systems designed for space applications. To achieve reliability, redundancy (memory sparing) is employed. Redundancy of memory may be achieved by duplicating memory completely or by adding additional rows or columns of memory to the basic minimum memory required by the system.
Typical computer memory is implemented in semiconductor chips having a particular storage capacity and organization. One such memory organization may be a chip having a 128K (K=1024) by 8-bit memory words. When a particular word of this memory is addressed, 8 bits are read from the memory or written to the memory at the appropriate address. Each memory word is 8 bits in width. Larger memories may be formed by including more memory chips in rows and columns. That is, if a 32-bit wide memory word is desired, the memory may include a row of four such memory chips, each memory chip providing 8 bits of data in or out. When each of these four memory chips is simultaneous enabled and the appropriate address entered, a memory word 32 bits in width is produced at the output of these four memory chips. To provide a greater number of memory words for the computer system, additional rows of memory may be included. Each memory row would produce a 32-bit data word, for example.
For reliability using a redundant approach, another row of memory may be provided. That is, a number of memory chips would have to be added equal to the width of the basic computer memory word of the system. In the above example, for a 32-bit word, a row of four memory chips would be added. When the computer fault detection mechanism detected a fault in one of the memory chips, the whole row of chips in which that memory fault resided would be disabled. The whole row of memory chips held as redundant spares would then be enabled to replace the faulty memory row. This is an inefficient scheme since for one memory chip failure many memory chips would be required to replace the entire row in which that failure occurred.
Column redundant memory is a more efficient arrangement. For column redundant memory, one memory chip for each row of memory is added in a column. The column of added memory chips each may serve as a replacement for a faulty memory chip with the stipulation that only one fault in each row is obtained. The benefit is that if a fault exists in one memory chip of four different rows, each of these memory chips may be replaced with a spare memory chip under the column sparing approach.
It is highly desirable to provide an efficient column sparing memory arrangement for a computer memory system which is easy to manufacture.